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MK2705
Audio Clock Source
Description
The MK2705 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source with a 27 MHz crystal. The device uses the latest PLL technology to provide good phase noise and long term jitter characteristics in a small 8-pin package. Contact ICS if you have a requirement for an input and output frequency not included in this document.
Features
* * * * * * *
Packaged in 8-pin (150 mil wide) SOIC Clock or crystal input Low phase noise Low jitter Exact (0 ppm) multiplication ratios Independent output voltage Support for 256 times sampling rate
Block Diagram
VDD
VDDO
S0 S1 X1/REFIN 27 MHz crystal or clock input
Crystal Oscillator
PLL Clock Synthesis and Control Circuitry
CLK
X2 GND
Optional crystal load capacitors
MDS 2705 C
1
Revision 102103
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
MK2705 Audio Clock Source
Pin Assignment
X1/ REFI N VDD S0 GND 1 2 3 4 8 7 6 5 X2 VDDO S1 CLK
Output Clock Selection Table
S1
0 0 1 1
S0
0 1 0 1
Input Frequency (MHz)
27 27 27 27
Output Frequency (MHz)
8.192 11.2896 12.288 24.576
8-pin SOIC
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8
Pin Name
X1/REFIN VDD S0 GND CLK S1 VDDO X2
Pin Type
Input Power Input Power Output Input Power Input
Pin Description
Connect this pin to a 27 MHz crystal or clock input Power supply for crystal oscillator and PLL. Output frequency selection. Determines output frequency per table above. On-chip pull-up. Connect to ground. Clock output. Output frequency selection. Determines output frequency per table above. On-chip pull-up. Power supply for output stage. Connect this pin to a 27 MHz crystal. Leave open if using a clock input.
MDS 2705 C
2
Revision 102103
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
MK2705 Audio Clock Source
Application Information
Series Termination Resistor
Clock output traces should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line and as close to the clock output pin as possible. The nominal impedance of the clock output is 20. nominally required crystal load capacitance. To reduce possible noise pickup, use very short PCB traces (and no vias) been the crystal and device. The value of the load capacitors can be roughly determined by the formula C = 2(CL - 6) where C is the load capacitor connected to X1 and X2, and CL is the specified value of the load capacitance for the crystal. A typical crystal CL is 18 pF, so C = 2(18 - 6) = 24 pF. Because these capacitors adjust the stray capacitance of the PCB, check the output frequency using your final layout to see if the value of C should be changed.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the MK2705 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the MK2705 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation.
PCB Layout Recommendations
Observe the following guidelines for optimum device performance and lowest output phase noise: 1) Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The external crystal should be mounted next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI and obtain the best signal integrity, the 33 series termination resistor should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the MK2705. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Recommended Power Supply Connection for Optimal Device Performance
Ferrite Bead VDD Pin VDD Pin
Connection to 3.3 V Power Plane
Bulk Decoupling Capacitor (such as 1 F Tantalum) 0.01 F Decoupling Capacitors Both VDD pins m be connected to the sam voltage. ust e
Crystal Load Capacitors
If a crystal is used, the device crystal connections should include pads for capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the
MDS 2705 C
3
Revision 102103
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
MK2705 Audio Clock Source
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2705. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 4.5 V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 175C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.0
Typ.
Max.
+70 +3.6
Units
C V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70C
Parameter
Operating Voltage Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Supply Current Short Circuit Current Nominal Output Impedance Input Capacitance Internal pull-up resistor value
Symbol
VDD VDDO VIH VIL VOH VOH VOL IDD IOS ZOUT CIN RPU
Conditions
Min.
3.0 1.8 2
Typ.
Max.
3.6 VDD 0.8
Units
V V V V V V
IOH = -4 mA IOH = -20 mA IOL = 20 mA No Load Each output Input pins
VDD-0.4 2.4 0.4 24 65 20 7 120
V mA mA pF k
MDS 2705 C
4
Revision 102103
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
MK2705 Audio Clock Source
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature 0 to +70 C
Parameter
Input frequency Output duty cycle Output clock rise time Output clock fall time Jitter, short term Jitter, long term Frequency synthesis error Single sideband phase noise
Symbol
tOD tOR tOF
Conditions
VDD/2, Note 1 20% to 80%, Note 1 80% to 20%, Note 1 peak to peak, Note 1 10 us delay peak to peak, Note 1 10 kHz offset
Min.
45
Typ.
27 49 to 51
Max.
55 1.5 1.5
Units
MHz % ns ns ps ps ppm dBc
175 300 0 -110
Note 1: Measured with 15 pF load
MDS 2705 C
5
Revision 102103
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
MK2705 Audio Clock Source
Package Outline and Package Dimensions (8-pin SOIC, 150 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
8
Inches Min Max
Symbol
Min
Max
E INDEX AREA
H
12 D
A A1 B C D E e H h L
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
.0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8
A A1
h x 45 C
-Ce
B SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
MK2705S MK2705STR
Marking
MK2705S MK2705S
Shipping packaging
Tubes Tape and Reel
Package
8-pin SOIC 8-pin SOIC
Temperature
0 to +70 C 0 to +70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 2705 C
6
Revision 102103
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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